The present invention relates to a time base correcting circuit for removing a time base error contained in a memory stored signal which signal is read out from the memory and, more particularly, to a time base correcting circuit for a digital video tape recorder.
In a digital video tape recorder ("VTR"), a video signal is converted into a digital video signal. The digital signal is in the form of a data train, divided into data blocks each containing about 200 to 1,000 bits of data A synchronizing signal having a predetermined bit pattern and a synchronizing address for identifying each block are added to each data block. A predetermined number of blocks are combined to form one sector. As a result, a periodic signal format in which the sector is repeated is formed. The sectored digital signal is recorded on a magnetic tape.
An error detection code may be added to the synchronising address. Generally, in recording and reproducing in a VTR, a time base fluctuation occurs which can produce a time base error in a reproduced signal. Such time base error is removed by a time base correcting circuit ("TBC"). In a digital VTR, an output signal of the TBC is supplied to an error correction process in which an error of data is corrected by using an added error correction signal such as a CRC code, and a D/A converting process to obtain an analog video signal.
The operational characteristics of the TBC are such that, as is well known in the art, a reproduced signal from the VTR is written in a memory in a write-in address synchronized with a clock which is extracted from the reproduced signal and which contains the time base fluctuation. Next, the stored signal is read out from the memory on the basis of a read-out address which is synchronized to a reference clock which is free from the time base fluctuation. In the TBC of the digital VTR, the write-in address is produced on the basis of the respective synchronizing address of each block, which synchronized address is extracted from the reproduced signal. Therefore, if the synchronizing address extracted from the reproduced signal is erroneous or an error is introduced in the extracting process, the respective block data linked to the erroneous synchronizing address will not be written in the correct memory locations and incorrect images are reproduced.
In the prior art, therefore, an error detection code is added to the synchronizing address to verify the correctness of the synchronizing address. When the synchronizing address is erroneous, the writing operation of the block data is inhibited. The TBC described above is disclosed, for example, in U.S. Pat. No. 4,398,224 entitled "Time Base Correcting Apparatus" issued Aug. 9, 1983.
If the writing operation is inhibited in the TBC because of the detection of the erroneous synchronizing address, the video data error correction process which follows the TBC, causes a data block from one of the preceding periods to be read out instead. Or a block data corresponding to the block inhibited from being written is not obtained. Thus, a characteristic of the error correction in the error correcting process becomes lower. This results in degradation of the quality of the reproduced video signal.